So what's the problem with yesterday's solution?
The growth in size and complexity of FPGA technology has created a gap in the typical printed circuit board design flow. If you study the design flows recommended by your FPGA vendors and your EDA suppliers, you see that their idea of automation centers around completing the programmable logic design, then importing the results into your PCB flow.
Historically, this flow had merit because the pinout changes caused by successive place and route (P&R) iterations raised havoc as those changes migrated through to the schematic and board layout flows. Locking down your pinout prematurely was risky and often was time consuming as the ability to route the PLD to predetermined pinouts was more black art than algorithm. Also, the pin counts on PLDs was relatively small so creating a symbol for an FPGA or CPLD was easily accomplished.
Today, the FPGA may be the most complex piece of logic on the board with pin counts that may exceed 1000 pins. FPGA coding can easily be the largest block of time in your project schedule. For most, delaying the design of the PCB until the programmable logic has been completed is not an option. Fortunately, FPGA tools can now reliably use pin assignments specified in the user constraints file(UCF). Pins assignments can now be made early in the design process with the confidence that they will not change due to tool issues.
Oleda Symbols
When you log in to the Oleda Symbol Generator, you immediately see the 4 steps to downloading your symbols. Completion of each step will return us to this screen with the next step enabled. We will start a new project by clicking "Read in Design Data".
Oleda provides the option of creating schematic symbols customized to your design, or creating generic symbols that can be used in any design. If you have a design that has been placed and routed, selecting the "PAD" file from the Xilinx tools is a good option. Reading the pad file insures that we have all of the design signals with their IO standards and direction.
If the design is not complete, but you have a UCF file with pin names and assignments, read the UCF file to verify the pinouts and signal assignments make sense.
Haven't worked out the signal assignments but want to get started on the board? You need a 'generic' symbol. Just pick your part from the selection windows and "Set the part". You can go ahead create a symbol for your board designs without any additional data sources.
Once we either load from your design data or set the part for a generic symbol, we come back to the main window. You can see the check mark indicating that we have read in the design data. The link for configuring the symbol set is now enabled.
The Oleda tools create a heterogeneous symbol set to represent the FPGA. Heterogeneous symbols are a group of symbols, each different, which when taken as a group, completely represent the whole part. When we 'Configure' the symbol set, we will be controlling how many symbols to divide the part into, and setting some naming options for the pins.
When we begin configuring a new symbol set, we must determine if the symbol set will be for one part-package combination only, or if the symbols should represent all of the parts that are foot-print compatible to this package. Please see how Oleda can generate Common-Footprint Symbols. For this tutorial, we will skip that step.
The symbol configuration screen has configuration controls located above the status tables. When an option is set, the results of that action can immediately be observed. The table on the left lists each of the sections in the symbol set and the number of pins located on the symbol for that section. When you click on a symbol name, the signal contents for that symbol are listed in the table on the right.
Configuration Options:
- VCCO pins can be placed on the IO bank or on the Power and ground symbol.
- No connect pins can be moved to separate symbol or left with the IO banks.
- Configuration pins can be selectively moved to the configuration symbol, or left with the IO pins.
- By default, Oleda creates a separate symbol for each IO bank, a configuration symbol and a power and ground symbol. If the part has MGTs, a pair of MGTs are put on a symbol. Oleda can also split signals onto separate symbols based on the names of signals. This example has signals that begin with 'USB_'. All the signals with a common prefix can be located on their own unique symbol which creates functional symbols. A symbol with the SDRam interface can be located near to your SDRam on the schematics. Your PCI connector can be close to the PCI interface for the FPGA.
When we return from configuring the symbols, links to both steps 3 and 4 are enabled. We can view the symbol templates using the Oleda symbol editor, or we can skip that step and download the symbols.
The Oleda Symbol Editor requires the Sun Java Plugin to be installed in your browser. This graphical editor allows you to reposition pins on a symbol, or to drag and drop pins to another symbol on the part. Each of the symbols is displayed in the 'filmstrip' along the bottom of the applet. Clicking on an image will bring it into 'focus' and edit mode. Multiple symbol sets can be created and saved for any given project.
Up to this point, the symbols were actually templates for the symbols. When we click 'Generate Symbols', we will create the symbol files for ViewLogic, and an EDIF file describing the Orcad library component. We can also add custom attributes to the symbols. In this example, we have added the attribute named 'DBLINK' and set its value as 'xilinx_3S400FG456-7'. Typically, these attributes are for BOM management functions which are unique to the company design flow.
ViewLogic symbols are combined into a 'ZIP' archive for easy downloading. They are archived in a 'sym' directory. Once you download and decompress your file, you can copy them to your project directory or other storage location. The Orcad EDIF is one large text file which contains the descriptions of all the parts. When you run Capture's IMPORT EDIF command, Orcad will create a standard 'OLB' library file for your symbol.
| ©2004 Oleda Technologies | 978-223-2213 |
