Oleda tools are accessed by logging into to a SSL encrypted web site. Our FPGA design tools are focused at the IO pins and their connections to your circuit board. Typically, you load your user constraints file (UCF) or your PAD report from the Xilinx place and route tools which tell us the signal names and pin assignments for your design. Once your design has been loaded, you can use our tools to generate schematic symbols and documentation or check the FPGA connectivity to your board.
FPGA vendors often offer multiple parts in a given package. They maintain common power and ground pin assignments across the parts and keep the configuration pins in the same location. As a user, this allows you the flexibility of removing features from your design to save production costs, or to add new functions in a larger part without having to change your PCB. The Oleda Migration planner helps you maintain this flexibility in your design.
Today, larger FPGAs have over 1700 pins. Manually entering pin information while creating symbols is a time-consuming and error prone process. Simple omissions and typing errors can lead to costly debug time and board spins.
The flexibility offered by multiple IO standards, different configuration options and high-speed serial links might mean more things that can go wrong when you hook up to your board. See how Oleda Connections provides more checks and assurances than simple DRC checking routines.
Hate creating documentation? See how Oleda routines can consolidate your design information in convenient packages that you can use stand-alone, or incorporate into Word or other word processors.
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