Symbols for Multiple Parts

Creating Schematic Symbols for Common-Footprint Parts

When Xilinx offers a family of different sized parts in the same package, they make sure the dedicated pins such as power, ground, configuration and JTAG are located on the same pins for each of the parts. These different parts are referred to as having a common footprint. In some families such as the Virtex 2, Xilinx made the pinout of the FG456 package a subset of the larger FG676. Essentially, if you add two rows of pins around the FG456 pinout you create the FG676 pinout. This technique is discussed further in the Xilinx Xcell article, Footprints in Silicon. With the dedicated pins already matched, you as an FPGA designer, must focus on making the user IO assignments match across the parts in your migration path.

From the PCB layout point of view, you must create a layout symbol for your footprint that contains the union of pad locations from each part that fits your footprint. In the case of this image, your layout symbol needs to have locations for all the green pads and all the red pads. At the schematic level, an additional constraint must be met. We need the ability to distinguish which IO pins are available in all the supported parts (the green pins) and which IO pins are only connected on a subset of the total group (the red pins).

We used the Oleda Migration Planner to identify the pins common to the FG456 and FG676 packages for the Virtex 2 family and create this image.

This article assumes that your are familiar with Oleda's Symbol generator. Creating a set of heterogeneous symbols for multiple parts adds only one additional step to the Oleda tool flow. When you click on 'Configure Symbol Set' from the main screen, you are asked to choose between creating a symbol only for the design's current part-package combination, or creating a symbol set for the parts that share a common pinout with that part.

Choosing to support multiple parts will launch the following applet:
This applet allows us to create customized text for the pins on our symbols. The description gets rather confusing, so to see where we are headed, jump down to the end. Once you see the end, the steps in the middle will begin to make more sense.

A checkbox for each footprint-compatible part determines if you want to support that part with this symbol set. As each box is checked, a note is constructed for that part. Note#1 is always the smallest supported part in the checklist.
The pin numbers for each row are listed in the left column. In the case of subset packages, a column with the pin numbers for each package are provided.
A column for current signal assignments.
Each part that is footprint compatible with your design part is listed in its own column.
The last column contains the calculated pin text for the symbols to be generated.

The label for each pin is calculated as follows:

Use the pin description from the largest part in your checklist, in which the pin is connected, as your base label.
For each checked part, append the note number to the label if the pin is a NC in that part.
For Subset Packages, pre-pend the pin number of the smaller package to the label. The pin number of the larger part will be on the pin and in the netlist. If the smaller part is actually used in the FPGA, the UCF and FPGA documentation will all reference the smaller number, while the circuit board documentation will continue to use the larger number.

Once we save the settings, the remaining configuration steps are the same as a single part-package symbol set.

This is what we end up with.

The notes at the bottom of the package annotate the meanings of the pin labels. You can see the intended package support.
Pin G8 (top left) is an interesting case. The "*2,3" indicates that this pin is not connected in the 2V1500FG676 or 2V2000FG676. The base name came from the 2V1000FG456 since that was the largest part in which this pin was connected. In the 2V3000FG676, this pin is a part of bank 0, but in the FG456 parts, the pin is part of bank 7. The "(E6)" is the pin number for the FG456 package.
Pin B1, (fifth down on left), has no pin in parenthesis. Since B1 is located in the outer most row of pins, it is not connected to the FG456 part and therefore has no pin number for the smaller part.

Supporting common-footprint parts is a way to maintain the ultimate in flexibility throughout your product lifetime. Careful choice of IO assignments can gain additional options when expanding features, reducing cost or add purchasing flexibility over your product lifetime. Manually supporting these options can be tedious and error-prone. Oleda tools simplifies the process through the planning, implementation and documentation phases of your design.

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