Okay, you've just nailed down the part selection for your next FPGA design. You've chosen your vendor and the FPGA family that has the features you need, your FAE has helped you pick the right size part and manufacturing has helped you narrow the package selection. The vendor offers your part in multiple packages, and more importantly to you, they offer multiple parts in your chosen package. These parts provide the promise of a backup plan and the successful completion of your next FPGA based design. The Oleda Migration Planner lets you rapidly compare all the FPGA devices and their resources that are available in your chosen package. This tool will help you plan to use a range of FPGA parts in your product that won't require a respin of your printed circuit board.
Perhaps first, we should look at the advantages of resizing your design into a larger or smaller part.
- Compacting your design to a smaller part can save money and power. You may be able to move to a smaller part once a product feature is removed or fully defined, or perhaps functions can be implemented with fewer resources when more development time is available.
- A growth plan into a larger part may allow you to support marketing's mid-production feature request, without incurring the time and cost of a PCB respin.
- Using a larger part during development can save you time on each place-and-route iteration. P&R times are reduced when the availablity of routing resources is higher. You may also include additional test and debug circuitry into your hardware design for the development phase, then remove this circuitry for production runs in the smaller part.
- Smaller parts have fewer IO cells. This means that some package pins that are used for IOs in the larger parts are left unconnected in the smaller parts. Using these pins for critial IOs can prevent you from migrating down in size. If you inadvertently connect a signal to these pins while entering your board schemtatics, it can cost you money later on.
- Larger parts require more configuration memory. Failing to plan for configuring a large part limits your ability to migrate up to add features.
- More features and larger parts can tax your power and cooling resources.
In most cases, you can effectively manage these pitfalls or totally avoid them by planning ahead. Two examples illustrate the range of situations.
- For many designs, resizing a part is a part of the 'just in case scenario'. As a optimistic designer, you hope to be able to shrink your design into a smaller part, but the pessimist in you is reassured with the knowledge that a larger part could be used if needed. The differences in power requirements and cost incurred by shrinking or growing one part size are minimal. Your primary concern is that of pinout compatibility.
- At the other end of the spectrum, designers of prototype or demo boards are interested in creating board designs that allow the use of the widest possible range of FPGA sizes. Their products may be defined by the size of the FPGA on the board. Power and configuration concerns become a larger issue to be addressed, but pinout conflicts are paramount.
When Xilinx offers a family of different sized parts in the same package, they make sure the dedicated pins such as power, ground, configuration and JTAG are located on the same pins for each of the parts. These different parts are referred to as having a common footprint. In some families such as the Virtex 2, Xilinx made the pinout of the FG456 package a subset of the larger FG676. Essentially, if you add two rows of pins around the FG456 pinout you create the FG676 pinout. This technique is discussed further in the Xilinx Xcell article, Footprints in Silicon. With the dedicated pins already matched, you as an FPGA designer, must focus on making the user IO assignments match across the parts in your migration path.
Picking a Package
Figure 1 is a screenshot of the Oleda Migration Planner. For our example, we have chosen the Virtex2 family and then selected the XC2V1000 from the part field. As we narrow our choice of part, starting from the 'Vendor' on the left, each decision causes the entries in the select boxes to the right to be updated.
Figure 1. Choosing a Part in the Migration Planer
The table of Footprint Compatible Parts illustrated in Figure 1 shows the number of IOs, the DCMs, number of slices and flip-flops along with the block ram resources available for each part in the migration path. This table is updated with each package selection. The data displayed in this table is available from the vendor's selection matrix, but the Migration Planner display filters this information as you select a part, allowing you to quickly consider your options while saving you time and potential oversights.
The XC2V1000 is available in 4 different packages as shown in the 'Package' select list. Each package has its own electrical and heat dissipation characteristics that you as a product designer will consider, but that we choose to ignore here.
| Package | IO count | Common Footprint Parts |
|---|---|---|
| FG256 | 172 | 2V40FG256,2V80FG256,2V250FG256,2V500FG256,2V1000FG256 |
| FG456 | 324 | 2V250FG456,2V500FG456,2V1000FG456,2V1500FG676,2V2000FG676,2V3000FG676 |
| BG575 | 328 | 2V1000BG575,2V1500BG575,2V2000BG575 |
| FF896 | 432 | 2V1000FF896,2V1500FF896,2V2000FF896,2V3000FF1152,2V4000FF1152,2V6000FF1152,2V8000FF1152 |
Table 1 shows the IO count and the migration parts for each package in which the XC2V1000 is available. The parts in the migration path are ordered from smallest to largest with the XC2V1000 entry emphasized in bold. It is easy to see in the case of the FG256 package, there is no upward migration path available to us, as the 2V1000 is the largest Virtex 2 part available in the package. Conversely, in the FF896 and the BG575 packages, the 2V1000 is the smallest choice available and there is no downward path. The 2V100FG456 has footprint compatible part options in both directions.
Checking the Pins
Once we have a potential package chosen, we need to investigate the pin availablity for each of the footprint compatible parts. We will use the Oleda Footprint Viewer for the pin comparisons that follow. The Viewer displays a graphical representation of the LARGEST footprint compatible part/package in the migration path. It also displays a spreadsheet style table of each pin in the part. A short tutorial on the Footprint Viewer discusses the steps taken to get the following comparison values.
Table 1 shows the number of IO pins that are available for each XC2V1000 package option. This is typically the value considered when picking a part for a design. When you are planning a migration path, you also must consider the IO availability for the footprint compatible parts, and how many pins are in common with your target. In general, smaller parts have fewer IO cells. Table 2 shows the IO pins that are available in each footprint compatible part, and also how many of those pins are in common with the 2V1000FG456.
| Part | #IO | #IO in Common with 2V1000 |
|---|---|---|
| 2V250FG456 | 200 | 200 |
| 2V500FG456 | 264 | 264 |
| 2V1000FG456 | 324 | 324 |
| 2V1500FG676 | 392 | 247 |
| 2V2000FG676 | 456 | 297 |
| 2V3000FG676 | 484 | 324 |
Observe in Table 2 that while the XC2V1500FG676 has more IO pins available,(392), than either the XC2V1000FG456(324) or the XC2V500FG456(264), the number of pins the XC2V1500FG676 has in common with the XC2V1000FG456, 247 is fewer than the the number of pins the XC2V500FF456 has in common with the XC2V1000FG456, 264. This implies that when a board is designed to accommodate both the 1000 and 1500, a designer will have fewer IO pins available for the design than if he were targeting the 1000 and 500. When the board is designed to accommodate all three parts, the common IO count is 198 pins.
These comparisons and the following screen shots are from the Footprint Viewer. The green locations in Figure 2 are IO pins that are common between the 2V500FG456, 2V1000FG456, 2V2000FG676 and the 2V3000FG676. The red areas indicate pins that are not available as IO in one or more of the targets. When the 2V1500FG676 is included, 50 more pins are removed from consideration as shown in Figure 3.
To maintain our ability to change the size of the FPGA after we have fabricated the circuit board, we want to avoid assigning signals to any of the red pins.
Prohibiting the Pins you want to avoid
Once you have identified the pins that you don't want to use, you need to tell the tools not to use them. In Xilinx you do this by creating 'CONFIG PROHIBIT' statements in the UCF file. The Footprint Viewer will generate these statements along with a comment noting the description of the pins function. Because this this migration path includes multiple packages, the tool will generate a set of 'Prohibits' for parts in the FG676 package and a set for the FG456 parts.
# adding prohibits for FG456 CONFIG PROHIBIT = R5 ; # FG456 version of U7 IO_L54P_6 CONFIG PROHIBIT = W15 ; # FG456 version of AA17 IO_L69N_4 CONFIG PROHIBIT = AA16 ; # FG456 version of AC18 IO_L54N_4 CONFIG PROHIBIT = V16 ; # FG456 version of Y18 IO_L52N_4 CONFIG PROHIBIT = U20 ; # FG456 version of W22 IO_L21N_3/VREF_3
At this point, we have instructed the FPGA tools not to use these pins. We could also have highlighted and prohibited the use of pins that support other functions such as DCI reference pins, VREFs or Configuration pins.
Assigning the Pins you want to use
Ultimately the each signal in your design will be assigned to a pin. You will add these pin assignments to your UCF file to ensure that successive runs of your place and route tools will produce pin assignments that are consistent with your board design. There are several approaches that can be used to make these pin assignments. They can be tried individually or in combination to arrive at a pinout that is acceptable.
- You can let the tools pick the pins. When no specific constraints have been set for a pin location, the tools will place the pins in any available IO pin that has not been 'prohibited'. This generally produces pinouts that are less than optimal.
- You can use PACE to graphically assign pins. This Xilinx tool will read your UCF and top-level HDL file, and let you place signals onto the package. When complete, PACE will write out a UCF file with your new assignments.
- You can edit the UCF file and make pin assignments manually.
Regardless of the method of creation, you can graphically view the pin placements of your UCF file and make custom schematic symbols with Oleda's Boardlinx software.
Some Advanced Techniques
Assigning pins is relatively easy when the parts in your migration path have more common IO pins than are needed by your FPGA design. When your design requirements are close to or exceed the common pin count, the following approach can be used to support a few more pins across your migration path.
- Assign some priorities to the signals in your design.
a)Identify signals that MUST be in even a reduced functionality version of the design.
b)Identify signals that could be left out of a reduced functionality version. These signals might be lines that drive LEDs, static signals that configure options for other board circutry or test ports for development and debug. They might even be the LSB bits of buses to DACs or ADCs. - Use the footprint viewer to identify IOs that are connected in your target part, but are NC in one or more of the parts in your migration path.
- Assign your higher priority signals(1a) to the IO pins that are in common across your migration path. Assign lower priority signals(1b) to IO pins that are NC on the alternate parts. Add pullup or pulldown resistors to the schematic to place these signals in a known state when an alternate sized FPGA is used on the board. The resisitors can be left unpopulated during normal production of the board.
One advantage we offered for planning a migration plan included the ability to use a larger part during development and debug. Besides having quicker place and route times, it also offers the advantage of having access to additional IO pins for test ports. In our 2V1000FG456 example, we find that the 2V1500FG676 has 145 pins that are not connected in the 2V1000FG456. We can attach these pins to a connector for logic analyzers, pattern generators or daughter cards that can provide monitoring and stimulus functions during product development. In production, these connectors and pads will remain unpopulated.
Summary
In this article, we have discussed how with careful planning you can maintain the extra flexibility of changing the size of your FPGA without having to respin your circuit board design. This flexibility can be used to provide additional test and debug resources to speed development, or to save money during production. We have also shown how the Oleda Migration Planner can help specify the various combinations of IO pins that will gain you the most flexibility.
For further information on Oleda products, please contact Oleda through our web page or call 978-223-2213.
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