Oleda Connections

Oleda Connections brings an FPGA focus to PCB design rule checking. With programmable logic, it is not enough to just check to see if there is a connection to a pin. We need to check groups of pins with the understanding of the unique functionality they may have.

Connections checks your PCB netlist, one FPGA at a time. When you specify the Reference Designator for the part, we pull all of the connections to that part and begin a comparison with the information from your design. You can choose which tests to run and which to skip, ultimately though, you'll want to have a clean slate through the whole test. We briefly discuss the tests, but to see how it works on your design, contact Oleda for a trial account.

Power and Ground Checks - Checking the fix voltages such as Ground, VCCINT and VCCAUX is relatively straight forward. Oleda checks the net for each pin in the group. We expect all the pins in the group to be connected to the same net. The FPGA family dictates the voltage value for the power rail. We report the net name and the connection status for each power rail.
The VCCO and the VREF voltage values are based on IO standards implemented in the particular bank. Oleda scans all of the signals in each bank. If IO standards are found with conflicting VCCO or VREF requirements, those conflicts are reported. Finally, each of the VCCO power pins are examine for connectivity. We expect all the power pins to be connected to the same net. The net name and the expected value is reported for each bank.
Oleda Connections attempts to examine the entire JTAG chain in which the FPGA is connected. We first identify and read the nets that the TMS and TCK signals are attached. We then begin tracing the FPGAs TDI pin. We first assume that this pin is driven by another device's TDO pin. We attempt to map the target device by comparing its TDO,TMS and TCK pins to our database. When we have a match on these three pins and can identify the TDI pin for the target, we will move down the chain and repeat the process. When we reach the end of the chain or parts that we can identify, we then repeat the process using our TDO pin and search for TDI pins on targets. Using this technique, we can map chains of FPGAs that are linked together with JTAG. We finally graph out our results:
We begin checking Configuration pins with the Mode pins. If we can identify the target configuration mode, we will report it and limit our tests to that mode. Otherwise, we will examine the connections of the dedicated configuration pins,the serial configuration pins, and finally the parallel configuration pins. If a pullup resistor is suggested for a pin, such as DONE, we will check for the existance of a resitor to the appropriate voltage rail.
Connections will check bus signals for connections to a common signal name followed by an equivalent bus index. We identify buses that are connected to non-bus signals, connections to flipped indices, indices out of order as well as missing connections or duplicated connections.
Oleda will check for the presence of a resistor to ground or bank VCCO for the DCI pins. It also checks to see if any DCI standards are utilized in your design.
Connections looks for differential signals based on the positive and negative marker specified by the user. If we find a pair of signals with these markers, in the same location in the net name, we assume the pair to be differential signals. We check to see that the pins to which these nets are connected are part of the same differential pair. We also check the IO standards for the pins to verify that a differential IO standard has been specified.
MGT signals are checked as an MGT group. We attempt to verify the voltage required. We examine if the MGT is used, if so we check to see that the power pins are connected to one node, which feeds from the supply filters.
Oleda also checks for signals attached to the FPGA, but not declared in the pad or UCF file. We report any specified IO signals which are not connected at the board level.

Oleda Connections can't guarantee your FPGA design is going to work, but it can help catch the oversights and errors that creep into a design when you are under a deadline.

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