Oleda License Request

Trial License Request

Don't see the support for your FPGA vendor or EDA tools? We may have it in the works on one of our development platforms already. Let us know what you need!

The information requested here helps us target the design flows and vendors that we need to support. This information will not be sold, transferred or disclosed in anyway that will identify you as the source of the data. Only the fields marked with an asterisk (*) are required for a license.

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Re:			Promo Code:
FPGAs used:	Altera	Xilinx	Other:
Schematic Tools:	Orcad	ViewDraw	Other:
Message:	Please use this space for comments or features you would like to see in design tools. Also, when would be the most convenient time for you to have the demonstration?

What happens next?

One of our developers will get an email with the information you just entered. We'll contact you if we are missing info or have a question, then enter your information into our license database. Our license manager will email you with a password for your account. The initial license will be good for 1 week. If you login after that time, we will grant an automatic extension of 1 week, but we will also suggest that placing an order would be a great idea.

What makes a good trial for design tools?

We think this is a fair question, and we have some suggestions. Some people think we're crazy to offer full featured versions of our tools on a trial basis. Perhaps we are, but we don't know how we'd evaluate tools that we'd consider purchasing if we couldn't give them a try. Here are some things to consider and try:

Look at an old project that you have completed.
Load up the PAD or final UCF file for that design. When you look at the PadView, would you have made changes to the pin assignments, if you could have seen the view you have now? Are your bussed signals in close proximity, or are they scattered?
Make a set of symbols for your part. How long did you last set take? Did you resist making changes, because 'it takes too long'? Did you have a decent cross-reference list for your symbols?
You probably had to do some probing in debug and test, did you have an accurate pin list? If you added some probes for debug, was it easy to find the appropriate pins to bring out a signal? Were people happy with your design documentation?
Run your board netlist through our DRC program. Did you find issues in debug that we missed? Please tell us about them so we can add the checks that you need. Did we find things that you missed?
Finally, let us know what you think! If we are missing features, let us know!

978-223-2213